The present invention relates generally to systems and methods for fabricating integrated circuits (ICs) and more particularly to systems and methods for selectively setting fuses during IC fabrication.
Numerous types of electronic devices employ electrical circuits implemented as one or more integrated circuits (ICs). ICs are configured to achieve desired functions, for example, control of associated devices, digital-to-analog (D/A) or analog-to-digital (A/D) conversion, mixed signal analysis, amplification etc. The particular use and performance of a given IC often is dictated by accuracies achieved during manufacture.
Several different parameters can affect the performance of ICs fabricated on wafer die. In analog amplifier circuits, for example, such parameters can include open loop gain and dominant pole locations within the circuits. Open loop gain is functionally related to resistor values, and dominant pole frequencies generally depend upon capacitors, resistors and transistor characteristics in the circuits.
By way of illustration, resistor values that can vary across a wafer include contributions from sheet resistance and head resistance. Lithography and etch based factors also can affect variations in the patterned width of the resistor, which can further vary the resistance. All of these factors can influence the open loop gain and/or dominant pole frequency of ICs, which ultimately affects device performance. For example, sheet resistance can vary by ten to twenty percent, and variations in head resistance can also vary by an additional ten to twenty percent. Such variations can result in large deviations in open loop gain and/or dominant pole frequencies.
These and other variations in circuit parameters further can vary across different die fabricated in the same wafer as well as between different wafer lots. Conventionally, variations in amplifier parameters are accounted for by compensating all circuitry fabricated on a wafer in a like manner, which often leads to overcompensation for many of the ICs. For example, one or more selected parameters can be measured at one location on a wafer, which measured parameter(s) are utilized as a basis for configuring all circuitry derived from the wafer. Fuses can be blown for each wafer die to provide compensation for each of the ICs based on the single measurement taken. Such an approach presumes uniformity across the wafer and usually sets fuses for all ICs based on the measurement, typically assuming a worst-case scenario for a maximum variation in parameter values.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a system and methodology for fabricating integrated circuits (ICs) on die spread across a wafer. One or more parameters that can affect the performance capabilities of the ICs are monitored at die locations. The monitored parameters are utilized to determine one or more respective parameters for unmeasured die locations, such as by interpolating parameters for measured die locations. Selective fusing can then be implemented to configure the associated ICs at die locations based on the parameters associated with respective die locations. For example, the fusing can be utilized to disconnect circuit elements (e.g., capacitors) as well as to enable circuit elements (e.g., resistors or inductors) in the ICs.
According to one aspect of the invention, a method is provided to facilitate fabrication of integrated circuits (ICs) on a wafer. The method includes measuring electrical characteristics associated with at least some of the die locations on the wafer and computing at least one respective parameter value based on at least some of the measured electrical characteristics. One or more respective parameter value for unmeasured die locations can be determined based at least in part on at least one of the parameter values computed for the measured die locations. Fuses then can be selectively set at the die locations based on one or more of the respective parameter values for the respective die locations to selectively configure ICs at the die locations.
According to another aspect of the present invention, a system is disclosed that facilitates fabrication of integrated circuits (ICs) on a wafer. The system includes a measurement system that monitors electrical characteristics at select die locations, such as at locations spaced apart and across the wafer, and that determines one or more parameters for the measured die locations. Corresponding parameters also are determined for unmeasured die locations based at least in part upon parameters associated with the measured die locations. A fuse system selectively sets fuses at the die locations based on one or more parameter values for the respective die location to selectively configure ICs at the respective die locations accordingly. For example, the fuse system can set fuses to modify die structure by connecting impedance elements (e.g., capacitors, inductors, or resistors) at a desired node of ICs on respective die locations, such as to improve performance characteristics of ICs based on the parameters associated with the respective die location.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.